By Yongquan Fan
High-Speed Serial Interface (HSSI) units became common in communications, from the embedded to high-performance computing structures, and from on-chip to a large haul. trying out of HSSIs has been a not easy subject as a result of sign integrity concerns, lengthy try time and the necessity of pricey tools. Accelerating attempt, Validation and Debug of excessive velocity Serial Interfaces presents cutting edge attempt and debug ways and particular directions on tips on how to arrive to functional try of contemporary high-speed interfaces.
Accelerating attempt, Validation and Debug of excessive pace Serial Interfaces first proposes a brand new set of rules that permits us to accomplish receiver try out greater than a thousand instances speedier. Then an under-sampling dependent transmitter try scheme is gifted. The scheme can appropriately extract the transmitter jitter and end the full transmitter try out inside of 100ms, whereas the try frequently takes seconds. The booklet additionally offers and exterior loopback-based trying out scheme, the place and FPGA-based BER tester and a singular jitter injection method are proposed. those schemes might be utilized to validate, try out and debug HSSIs with information fee as much as 12.5Gbps at a reduce attempt price than natural ATE strategies. moreover, the ebook introduces an efficieng scheme to enforce excessive functionality Gaussian noise turbines, appropriate for comparing BER functionality below noise conditions.
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Additional info for Accelerating Test, Validation and Debug of High Speed Serial Interfaces
However, more loops also make the PLL design more complicated. To further improve the performance, there is also a trend to implement hybrid phase detectors. The hybrid approach presented in  exhibits the intrinsic advantages of low timing jitter in a linear PLL in lock state and the fast locking time in a BBPD PLL. Overall, there are many factors to consider when implementing a CDR and sometimes we have to make tradeoffs , ,  . Nevertheless, as there is a great pressure to characterize and test well the CDR whether it is implemented with a linear PLL or a BBPD PLL, it is desirable to devise testing schemes independent of the design style applied.
Figure 2-5 plots the binomial distribution with n = 108 and p = 10-7. If we treat the n as the total number of bits transmitted, p as the BER, and p n (k ) as the probability that k bit errors will occur, we can use the distribution to calculate the BER confidence level. We are interested in the probability that or fewer bit errors occur in n transmitted bits. The probability is the Cumulative Distribution Function (CDF) of the binomial distribution and is expressed as p (e ≤ n! p k q n−k k = 0 k!
If we know the DJ and the RJ, we can estimate the transmitter TJ as follows: TJ = DJ + 2Q * RJ where the Q factor is 7 at 10-12 BER. The above Q factor based transmitter TJ estimation is much faster than the direct measurements at lower BERs. We can also use the Q factor to accelerate the receiver jitter tolerance testing, as will be discussed in Chapter 3. Even though the Q factor is widely used in the industry , , the measurement accuracy may be affected if the RJ distribution deviates from the true Gaussian distribution .