A typical syntax and semantics for VHDL check in move point (RTL) synthesis is outlined. The subset of IEEE 1076 (VHDL) that's appropriate for RTL synthesis is outlined, besides the semantics of that subset for the synthesis area.
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Additional resources for 1076.6-1999 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
All rights reserved. 6-1999 IEEE STANDARD FOR VHDL Any after clauses shall be ignored. Multiple waveform elements shall not be supported. The value unaffected shall not be supported. Edge specifications (
That is, the expression shall be present in the constant declaration. b) Signal declarations signal_declaration ::= signal identifier_list : subtype_indication [signal_kind] [:= expression] ; signal_kind ::= register | bus Supported: — Signal_declaration Ignored: — Expression Not supported: — Signal_kind The initial value expression shall be ignored unless the declaration is in a package, where it shall have an initial value expression. The subtype indication shall be a globally static type. An assignment to a signal declared in a package shall not be supported.
6-1999 IEEE STANDARD FOR VHDL a) Record aggregates Not supported: — Record aggregates b) Array aggregates No restriction. 2. 6 Allocators allocator ::= new subtype_indication | new qualified_expression Not supported: — 42 Allocator Copyright © 2000 IEEE. All rights reserved. 1 Locally static primaries Locally static primaries shall be supported. 2 Globally static primaries Globally static primaries shall be supported. 5 Universal expressions Floating-point expressions shall not be supported. Precision shall be limited to 32 bits.